Panesia , a startup developing link solutions for AI infrastructure, was the only domestic company to participate in the CXL Developer Conference (CXL DevCon) this year, showcasing a high fan-out CXL 3.x switch-based framework. The CXL DevCon event was held in Santa Clara, California, USA on April 29th and 30th.
◆ CXL, the high-speed interconnect technology that is at the core of next-generation data centers
As large-scale AI services become widely used, the importance of building a computing infrastructure that can efficiently operate these services is increasing. In this situation, Compute Express Link (CXL), a high-speed interconnect technology, is receiving much attention as a key technology that enables the construction of an efficient next-generation computing infrastructure.
The main reasons why CXL is receiving so much attention are 1) reducing infrastructure construction costs and 2) minimizing performance overhead. First, CXL enables pooling, which manages various system devices by type. When a specific system device is insufficient, unnecessary resource waste can be minimized by selectively expanding only the pool where the devices are gathered (e.g., memory pool, GPU pool), thereby reducing infrastructure construction costs. In addition, since a CXL-based system automatically guarantees cache coherency, it minimizes operations for managing memory space and unnecessary data copying processes, thereby reducing the overall performance overhead of the system.
◆ CXL DevCon 2025
In this technological trend, CXL DevCon 2025 was held, providing a place to look into the present and future of the CXL ecosystem. CXL DevCon is an official event hosted by the CXL Consortium, which establishes the CXL standard, and this is its second year. CXL Consortium member companies leading the development of CXL technology, including Cadence, Teledyne LeCroy, and Panesia, participated and exhibited CXL products, and at the same time, experts leading the establishment of the CXL standard were invited to give presentations.
Panesia attracted the attention of various CXL specialized companies by presenting a CXL IP (design asset) interoperability verification demo at CXL DevCon 2024 last year, and participated as the only domestic exhibitor this year, presenting its flagship product, a high-power CXL 3.x switch, and a framework based on it.
◆ Panesia's entry: High-power CXL 3.x switch-based framework
The high-power CXL 3.x switch introduced by Panesia acts as a bridge that integrates different CXL devices into a single system with guaranteed cache coherence. In addition to being developed based on Panesia’s own low-latency CXL IP, it has a high-power SoC structure that can connect more devices at once, thereby minimizing latency by reducing the average number of hops in the system.
In addition, Panesia's switches support multi-level switching, which connects multiple switches in multiple layers, and port-based routing (PBR), which flexibly sets up logical connection structures and connection paths between devices based on the 'port', which is the physical location where each device is mounted. In addition, since it supports connections to all types of system devices, such as CPUs, GPUs, and memories, it is optimized for building large-scale systems that meet customer needs by connecting numerous system devices in various forms and combinations.
At this exhibition, Panesia exhibited the 'CXL Composable Server' built by connecting multiple CXL server nodes using these CXL 3.x switches. Each server node is equipped with CPUs, GPUs, and memory devices developed using CXL IP, another product of Panesia, separately by type. Therefore, customers can build a system in a form suitable for their needs by additionally installing nodes equipped with the necessary devices at that time. Panesia received a lot of attention from the CXL specialized companies attending the event by presenting a demo that accelerated AI applications and scientific simulations such as Retrieval Augmented Generation (RAG) and Large Language Model (LLM) based on the framework.
◆ Panesia Vice President Cho Yong-jin presents CXL 3.x switch usage case
Meanwhile, Vice President Cho Yong-jin of Panesia participated as a speaker in the official announcement session of CXL DevCon 2025. Through this presentation, Vice President Cho introduced various solutions that can be implemented based on the CXL 3.x switch and cases of accelerating actual data center and high performance computing (HPC) applications using them. He also discussed building the CXL ecosystem with key members of the CXL consortium.
A Panesia official said, “Panesia was the only one to present and exhibit CXL 3.x switch technology,” and “Since CXL 3.x switches are a new technology to the leaders of the CXL consortium, they seemed to be very interested in Panesia’s exhibit and presentation.” He continued, “We have had many discussions with companies that are directly developing CXL products or are highly interested in them, and we expect to be able to build a robust ecosystem through active collaboration with them.”
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